2PARMA Project eu fp7



A program intended to perform a specific task. An application includes an executable file that is invoked to run the desired program.

Application Mode

Ideally, for any application, all functionalities should be accessible at any time. However, based on the user requirements, the environment changes, the available platform resources, and the limited power budget of the platform, it may not be possible to integrate all these functionalities on the platform at the same time. Hence the application developer has to organize the application into application modes, each one specifying a different subset of functionalities.

Application Programming Interface (API)

Set of functions provided by an infrastructure that can be used by the application developers to program the application code.

Application-Specific Integrated Circuit (ASIC)

The common name for semi-custom integrated circuits. A type of chip that is composed of standard building blocks called cells that are designed to implement a specific customer application. These may include digital, linear, and mixed-level circuits.

Application Working Mode (AWM) or Operating Point (OP)

A set of application configurations identified by DSE and used to establish a sort of loose biding between application performance and resource requirements. Such, off-line recovered information is used at run-time, exploiting different levels of details, by the run-time resource management policies.

Automatic Design Space Exploration

Automatic version of the design space exploration. It works without the designer in the loop.


A design test case that is used to measure the capabilities, limitations, and breakthroughs reported for newly proposed and existing algorithms, architectures and tools.

Cycle accurate

A modeling style in which it is possible to predict the state of the model in any given cycle at the external boundary of the model and thus to establish a one-to-one correspondence between the states of the model and the externally observable states of a corresponding RTL model in each cycle, but which is not required to explicitly re-evaluate the state of the entire model in every cycle or to explicitly represent the state of every boundary pin or internal register. This term is only applicable to models that have a notion of cycles.

Design cycle

The period of time required completing an electronic design of any type, from concept to production.

Design entry

The process of creating a new design of any type chip, board, module, or system using textual and/or graphical tools such as schematic capture or other high-level graphical methods, hardware description languages, Boolean equations, or other methods.

Design flow

A series of connected processes used within the design cycle.

Design of Experiments (DoE)

Techniques that allow performing a smart exploration of the design space by extracting as much information as possible from a limited number of evaluations. They are used to identify the planning of experimentation campaign.

Design Space

Set of all possible design configurations.

Design Space Exploration (DSE)

Design phase used to evaluate different design alternatives by tuning the system parameters.

Design Space Exploration Tool

Tool that allows specifying and solving the exploration problem in terms of optimization metrics and constraints. Moreover it provides estimates of the optimal configurations of the use case and automatically interacts with the use case simulator.

Design-time Design Space Exploration

DSE phase done at design time to tune statically the system parameters.

Dynamic evaluation

Simulation based system evaluation.

Dynamic Memory Management (DMM)

The dynamic allocation and de-allocation of heap data to the systems heap(s). Such operations can be performed by the application through the invocation of standard API calls (malloc(), free() and realloc()).

Dynamic Voltage and Frequency Scaling (DVFS)

Is a technique in computer architecture whereby the frequency and/or the voltage of a HW component(s) can be (automatically or manually) adjusted on the fly, either to conserve power or to reduce the amount of heat generated by the chip.

Electronic system level (ESL)

The utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner.

Exploration architect

Designer responsible for interacting with the design space exploration tool, specifying and running optimization strategies for the target Use Case and analyzing the DSE results.

eXtensible Markup Language (XML)

Set of rules for encoding documents in machine-readable form. It is a textual data format oriented to emphasize simplicity, generality, and usability in the representation of arbitrary data structures.


A computing architecture for integrating products from multiple vendors which includes data representation, design data management, methodology management, a user interface, an extension language, and inter-tool communication.

Functional Level Model

It is a high-level model of digital systems where only the functionality of the different components and their interactions with each other is modeled. This model does not usually contain any timing information associated with communication or processing and hence this model simulates the fastest.

Hardware Abstraction Layer (HAL)

Part of the operating system that allows creating the rest of the OS independently from the underlying platform. It is modified when the OS is going to be executed in a different platform.

Hardware Metadata

The main purpose of platform hardware metadata is to support the description of a target platform in terms of device availability, their features and capabilities, control and monitoring interfaces and also the hierarchical relationship between them.

Hardware-dependent Software (HdS)

Part of the software highly dependent on the HW platform and that must be rewritten when the code is moved to another platform.

High-Performance Computing (HPC)

Uses supercomputers and computer clusters to solve advanced computation problems.

Instruction Set Simulator (ISS)

Simulator of a processor that reads binary code for that processor and executes the code instruction by instruction.


A reusable block of semiconductor intellectual property


XML format that can be used to define and describe electronic components and their interconnections. It is an IEEE standard developed to enable automated configuration and integration through tools.

Levels of abstractions

When a digital system is modeled, it can be modeled at various different level of abstraction. More close the model is to the real system, more accurate it becomes, but at the same time it simulates much slower. So various abstraction levels are defined in system models in order to make a trade-off between accuracy and simulation time.

Multi-dimension Multi-choice Knapsack Problem (MMKP)

The knapsack problem is a problem in combinatorial optimization: Given a set of items, each with a weight and a value, determine the count of each item to include in a collection so that the total weight is less than or equal to a given limit and the total value is as large as possible. If there is more than one constraint, we get the multi-dimensional knapsack problem.

Multi-objective Optimization (MOO)

Multi-objective optimization (or programming), also known as multi-criteria or multi-attribute optimization is the process of simultaneously optimizing two or more conflicting objectives subject to certain constraints.

Multiprocessor System on-Chip Architecture (MPSoC)

Single chip architecture composed of two or more processors usually targeted for embedded applications. It is used by platforms that contain multiple, usually heterogeneous, processing elements with specific functionalities reflecting the need of the expected application domain, a memory hierarchy (often using scratchpad RAM and DMA) and I/O components.


A means by which an application or user can customize the behavior or characteristics of a model instance when it is created. A parameter is set to a constant value during design entry

Portable Operating System Interface [for uniX] (POSIX)

Standards specified by the IEEE to define the application programming interface (API), along with shell and utilities interfaces for software compatible with variants of the Unix operating system, although the standard can apply to any operating system.

Quality of Service (QoS)

Is the ability to provide different levels of service at different application working modes or the level of service requirements/constraints to be achieved.

Real-Time Operating System (RTOS)

Operating system with Real-Time qualities, as small, bounded latencies, real-time services.

Register Transfer Level Model or RTL model

RTL model describes the electronic system in a high-level hardware description language that describes the registers of a system (and transfer of data between registers) at a low level of abstraction. VHDL and Verilog are examples of RTL languages.

Response surface modeling

It is a technique used to create mathematical models for the relationship between one or more responses and a set of input variables.

Run-Time Design Space Exploration

DSE phase done when the system is working. It is used to select the system parameters that are run-time tunable (i.e. working frequency and application mapping). A set of optimal configurations for the system is obtained at design time, while at run-time the best configuration is selected considering working conditions.

Run-Time Resource Manager (RTRM)

It is a module in charge of the management of the system resources at run-time.

Run-Time Situation (RTS)

A run-time event that affects the behavior of the application.


It is the executable model of the use case and it provides the value of the estimated metrics, for a specific configuration of the architecture

Simulation model

Simulation Model is a software-based model designed to replicate the timing and behavior of an IC design for the purposes of verification and debugging.

Software Defined Radio (SDR)

A radio communication system where components that have been typically implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) are instead implemented by means of software.

Software Metadata

A representation of the application behavior regarding resource requirements (e.g. memory footprint, requested heap size, dynamic data type operations, etc.)

Symmetric Multiprocessing

Involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.

Synchronous Data Flow (SDF)

A restriction of Kahn process networks (KPN), where nodes produce and consume a fixed number of data items per firing.

System metrics

Metrics describing the behavior of the whole system. They are obtained considering the system as a black box (also called output variables) and used to drive the design space exploration phase.


Set of C++ classes and macros which provide an event-driven simulation kernel in C++, which in certain aspects mimics the hardware description languages VHDL and Verilog, but more oriented to be used as a system-level modeling language.

Static evaluation

System evaluation based on analytical models

Task Concurrency Management (TCM)

An optimization methodology that explores the energy-performance trade-off at the system level. To reach an efficient usage of the platform resources, this methodology models the application at a finer granularity than traditional task graphs. It identifies the subtasks of the application that can run in parallel on a heterogeneous multiprocessor platform. It also includes data access and memory management at the task level.

Transaction level (TL)

The abstraction level at which communication between concurrent processes is abstracted away from pin wiggling to transactions. This term does not imply any particular level of granularity with respect to the abstraction of time, structure, or behavior.

Transaction level model, transaction level modeling (TLM)

A model at the transaction level and the act of creating such a model, respectively. Transaction level models typically communicate using function calls, as opposed to the style of setting events on individual pins or nets as used by RTL models. Moreover, It is a high-level abstraction model of digital systems where details of communication among different components are separated from the details of the implementation of functional units or of the communication architecture. This is used to explore different design architectures without the overhead of designing or simulating the details of how particular transforms may be implemented.

Use case

Combination of the target architecture and application running on it.

Use case and simulator provider

It is the user agent that has in charge to release the use case (architecture and application), the use case simulator program and the definition of the use case design space.

Virtual platform

Virtual platforms are software models of complete systems that provide software engineers with high-speed, pre-silicon development environments months before hardware is available. Virtual platforms enable concurrent development of hardware and software, significantly shortening embedded system suppliers hardware/software integration time and accelerating their products to market. Because they are based on software models, virtual platforms offer unmatched effectiveness for developing and debugging multi-core designs.